Logo
Login Sign Up
Current Revision

IEEE 896.2-1991

IEEE Standard Backplane Bus Specification for Multiprocessor Architectures: Futurebus+(R)
Best Price Guarantee
Instant

$198.00


Sub Total (1 Item(s))

$ 0.00

Estimated Shipping

$ 0.00

Total (Pre-Tax)

$ 0.00


or
Institute of Electrical and Electronics Engineers Logo

IEEE 896.2-1991

IEEE Standard Backplane Bus Specification for Multiprocessor Architectures: Futurebus+(R)

PUBLISH DATE 1992
PAGES 222
Document Preview
New IEEE Standard - Inactive-Withdrawn. Futurebus+ standards provide systems developers a set of tools with which high-performance bus-based systems may be developed. This architecture provides a wide range of performance scalability over both cost and time for multiple generations of single- and multiple-bus multiprocessor systems. This document, a companion standard to IEEE Std. 896.1-1991, builds on the logical layer by adding requirements for physical layer instantiation. Material in this document includes specifications for node management, live insertion, and profiles. It is to these profiles that products will claim conformance. Other specifications that may be required in conjunction with this standard are the following: IEEE Std 896.1-1991; P896.3, Futurebus+ Recommended Practices; P1212.x, Control and Status Register Architectures; IEEE Std 1194.1-1991, Electrical Characteristics of Backplane Transceiver Logic (BTL) Interface Circuits; and IEEE Std 1301.x, Metric Equipment Practices for Microcomputers.
SDO IEEE: Institute of Electrical and Electronics Engineers
Document Number 896.2
Publication Date April 24, 1992
Language en - English
Page Count 222
Revision Level
Supercedes
Committee Microprocessor Standards Committee
Publish Date Document Id Type View
April 24, 1992 896.2-1991 Revision